An integrated semiconductor memory, for example a DRAM (Dynamic Random Access Memory) semiconductor memory, comprises memory cells arranged in a memory cell array, constructed from rows and columns in a matrix form, between word lines and bit lines. A single DRAM memory cell comprises a storage capacitor which can be connected to one of the bit lines by a selection transistor. A control connection on the selection transistor is connected to one of the word lines. For read or write access to the DRAM memory cell, the selection transistor is turned on by actuating an appropriate control signal on the word line, so that the storage capacitor is connected to the bit line via the activated path of the selection transistor. Depending on the charge state of the storage capacitor corresponding to a logic information item stored in the memory cell, the bit line's potential rises or falls in comparison with a precharge potential to which the bit lines in the memory cell array have been charged, generally prior to read or write access. A sense amplifier connected to the bit line amplifies the generally small potential change on the bit line to produce a high or low voltage potential.
To control read and write access, the integrated semiconductor memory comprises control connections, address connections, and data connections. Various control signals applied to the control connections of the integrated semiconductor memory can be used to activate the integrated semiconductor memory for read access, for example. Address signals applied to the address connections of the integrated semiconductor memory can in this case be used to select a particular memory cell for read access. Following the read access, the data stored in the selected memory cell are available on the data connections for further processing.
FIG. 1 shows a state diagram for read and write access to one of the memory cells in a memory cell array. The figure shows the time profile for control signals /CS, /RAS, /CAS and /WE and for data signals DQ, applied to the control connections and data connections of the integrated semiconductor memory during a plurality of clock periods of the control clock signals CLK and /CLK.
During a first clock cycle of the control clock, the integrated semiconductor memory is activated for write access. To this end, a signal combination ACT, which is formed from respective pulses of the control signals /CS and /RAS, is applied to the control connections of the integrated semiconductor memory. Further, the signal combination ACT is characterized by a state change in the control signal /CS and in the control signal /RAS from a high signal level to a low signal level at the crossover point for the control clocks CLK and /CLK. At the end of the first clock cycle, the control signals /CS and /RAS change back from the low signal level to the high signal level. The selection transistors for memory cells in one row of the memory cell array are conductively connected to the connected bit lines at the end of this first clock cycle.
During a second clock cycle of the control clock, the signal combination WRITE, which is formed from combinations of states of the control signals /CS, /CAS and /WE, is applied to the control connections of the integrated semiconductor memory. At the crossover point for the control clocks CLK and /CLK, the control signals /CS, /CAS and /WE change state from a high signal level to a low signal level. At the end of the second clock cycle, the control signals change back from the low signal level to the high signal level. The effect of the signal combination WRITE is that, among the selection transistors which are on in the memory cells in one row of the memory cell array, only that selection transistor which is associated with one particular column is conductively connected to the associated bit line. The other selection transistors are turned off.
During a subsequent third, fourth and fifth clock cycle of the control clock, a data record DQ applied to the data connections is read into the selected memory cell.
During a subsequent sixth clock cycle of the control clock, the signal combination PRE formed from respective pulses of the control signals /CS, /RAS and /WE is applied to the control connections of the integrated semiconductor memory. At the crossover point of the control clocks CLK and /CLK, the control signals /CS, /RAS and /WE change state from a high signal level to a low signal level. At the end of the sixth clock cycle, the control signals change back from the low signal level to the high signal level. The signal combination PRE charges the bit lines of the memory cell array to a common precharge potential which is between a high voltage potential, corresponding to a (logic 1) and a low voltage potential (logic 0). The aim of precharging the bit lines to a common precharge potential is to prevent signal levels from an earlier read or write access operation which are present on the bit lines from influencing a subsequent read or write access operation.
In the next seventh clock cycle of the control clock, the selection transistors for memory cells in one row of the memory cell array are turned on again by the signal combination ACT.
During a subsequent eighth clock cycle of the control clock, the signal combination READ, which is formed from pulsed state changes in the control signals /CS and /CAS, is applied to the control connections of the integrated semiconductor memory. At the crossover point of the control clocks CLK and /CLK, the control signals /CS and /CAS change state from a high signal level to a low signal level. At the end of the eighth clock cycle, the control signals change back from the low signal level to the high signal level. Among the selection transistors which are on in one row of the memory cell array, the signal combination READ now turns on a selection transistor which is associated with a particular column address. The other selection transistors in the selected row are operated in the off state. The sense amplifier connected to the selected memory cell amplifies the rise in potential or fall in potential which has appeared on the bit line to produce a high or a low voltage level, respectively. The memory information which has been read out, is then supplied to a data connection and can be tapped off at that point for further processing.
The interval of time between turning on a selection transistor in the memory cell array, for example using the signal combination ACT during the seventh clock cycle, and a subsequent read command, for example using the signal combination READ during the eighth clock cycle, determines a “reading time” TRCD for the integrated semiconductor memory. The reading time TRCD, which is generally part of the specification of the integrated semiconductor memory, is a particularly critical time parameter for the speed of a semiconductor memory. The reading time TRCD required for read access has been reduced further and further in recent years as technological development has progressed. To ensure the reading time indicated in the specification, this time parameter is tested in various tests during the manufacturing process at wafer level and on the finished component when production has been concluded. The reading times which can be produced are now already below 12 ns in some cases. The circuit design alone can no longer guarantee such short times, since the reading times are highly dependent on process fluctuations. It is therefore absolutely necessary to test the reading times, especially since the production process still has the option of replacing memory cells in a semiconductor memory which infringe the prescribed time limit with redundant memory cells. However, conventional tester limitations, for example, speed restrictions, mean that present test systems often have only limited ability to continue reliable testing of the reading times which are becoming shorter and shorter from memory generation to memory generation.